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# =============================================================================
# SystemVerilog/Verilog Snippets - Organized by Category
# Author: Auto-generated
# Description: Comprehensive SystemVerilog, Verilog and UVM snippets
# =============================================================================

# =============================================================================
# COMMONLY USED SNIPPETS (Top Priority)
# =============================================================================

snippet sv_header
	//==============================================================================
	// File        : ${1:`expand('%:t')`}
	// Project     : ${2:Project Name}
	// Module      : ${3:`expand('%:t:r')`}
	// Author      : ${4:$USER}
	// Created     : ${5:`strftime("%Y-%m-%d")`}
	// Modified    : ${6:`strftime("%Y-%m-%d")`}
	//==============================================================================
	// Description:
	//   ${7:Brief description}
	//==============================================================================
	
	${0}


snippet tb
	\`timescale 1ns/1ps
	
	module ${1:`expand('%:t:r')`};
	
	    localparam int PERIOD = ${2:10};
	    
	    logic ${3:clk};
	    logic ${4:rst_n};
	    ${5}
	
	    // Clock generation
	    initial begin
	        $3 = 0;
	        forever #(PERIOD/2) $3 = ~$3;
	    end
	
	    // Reset generation
	    initial begin
	        $4 = 0;
	        repeat(2) @(posedge $3);
	        $4 = 1;
	    end
	
	    // DUT instantiation
	    ${6:dut} u_dut (
	        .clk($3),
	        .rst_n($4)${7}
	    );
	
	    // Test stimulus
	    initial begin
	        @(posedge $4);
	        ${0}
	        #1000;
	        \$finish;
	    end
	
	    // Waveform dump
	    initial begin
	        \$dumpfile("${8:`expand('%:t:r')`}\.vcd");
	        \$dumpvars(0, $1);
	    end
	
	endmodule: $1


snippet always_ff
	always_ff @(posedge ${1:clk} or negedge ${2:rst_n}) begin
	    if (!$2)
	        ${3}
	    else
	        ${4}
	end

snippet class
	class ${1:`expand('%:t:r')`};
	    ${2}
		
	    function new(string name = "$1");
	        ${3}
	    endfunction: new
		
	endclass: $1

snippet sequence_item
	class ${1:`expand('%:t:r')`} extends uvm_sequence_item;
	    \`uvm_object_utils($1)
		
	    // Transaction fields
	    rand bit [${2:7}:0] ${3:addr};
	    rand bit [${4:31}:0] ${5:data};
	    ${6}
		
	    // Constraints
	    constraint ${7:valid}_c {
	        ${8}
	    }
		
	    extern function new(string name = "$1");
	    extern function void do_copy(uvm_object rhs);
	    extern function bit do_compare(uvm_object rhs, uvm_comparer comparer);
	    extern function void do_print(uvm_printer printer);
	    extern function string convert2string();
		
	endclass: $1
		
	function $1::new(string name = "$1");
	    super.new(name);
	endfunction: new
		
	function void $1::do_copy(uvm_object rhs);
	    $1 rhs_;
	    if (!\$cast(rhs_, rhs))
	        \`uvm_fatal(get_type_name(), "Cast failed in do_copy")
	    super.do_copy(rhs);
	    this.$3 = rhs_.$3;
	    this.$5 = rhs_.$5;
	endfunction: do_copy
		
	function bit $1::do_compare(uvm_object rhs, uvm_comparer comparer);
	    $1 rhs_;
	    if (!\$cast(rhs_, rhs))
	        return 0;
	    return (super.do_compare(rhs, comparer) &&
	            (this.$3 == rhs_.$3) &&
	            (this.$5 == rhs_.$5));
	endfunction: do_compare
		
	function void $1::do_print(uvm_printer printer);
	    super.do_print(printer);
	    printer.print_field("$3", this.$3, $2+1);
	    printer.print_field("$5", this.$5, $4+1);
	endfunction: do_print
		
	function string $1::convert2string();
	    return $sformatf("$3=0x%0h, $5=0x%0h", $3, $5);
	endfunction: convert2string

# moved: assert to COMMONLY USED SNIPPETS
	assert (${1:condition}) else \$error("${2:Assertion failed}");

# moved: property to COMMONLY USED SNIPPETS
	property ${1:`expand('%:t:r')`};
	    @(posedge ${2:clk}) ${3:condition};
	endproperty: $1

# moved: sequence to COMMONLY USED SNIPPETS
	sequence ${1:`expand('%:t:r')`};
	    ${2}
	endsequence: $1

# moved: implication to COMMONLY USED SNIPPETS
	${1:antecedent} |-> ${2:consequent}

snippet uvm_agent
	class ${1:`expand('%:t:r')`} extends uvm_agent;
	    \`uvm_component_utils($1)
		
	    ${2:`substitute(expand('%:t:r'), '_agent$', '', '')`}_sequencer  sqr;
	    $2_driver     drv;
	    $2_monitor    mon;
		
	    uvm_active_passive_enum is_active = UVM_ACTIVE;
		
	    extern function new(string name = "$1", uvm_component parent = null);
	    extern virtual function void build_phase(uvm_phase phase);
	    extern virtual function void connect_phase(uvm_phase phase);
		
	endclass: $1
		
	function $1::new(string name = "$1", uvm_component parent = null);
	    super.new(name, parent);
	endfunction: new
		
	function void $1::build_phase(uvm_phase phase);
	    super.build_phase(phase);
	    
	    // Get configuration
	    if (!uvm_config_db#(uvm_active_passive_enum)::get(this, "", "is_active", is_active))
	        \`uvm_info(get_name(), "is_active not configured, using default UVM_ACTIVE", UVM_MEDIUM)
	    
	    // Always create monitor
	    mon = $2_monitor::type_id::create("mon", this);
	    
	    // Create driver and sequencer only in active mode
	    if (is_active == UVM_ACTIVE) begin
	        sqr = $2_sequencer::type_id::create("sqr", this);
	        drv = $2_driver::type_id::create("drv", this);
	    end
	endfunction: build_phase
		
	function void $1::connect_phase(uvm_phase phase);
	    super.connect_phase(phase);
	    if (is_active == UVM_ACTIVE) begin
	        drv.seq_item_port.connect(sqr.seq_item_export);
	    end
	endfunction: connect_phase

snippet uvm_driver
	class ${1:`expand('%:t:r')`} extends uvm_driver #(${2:`substitute(expand('%:t:r'), '_driver$', '_item', '')`});
	    \`uvm_component_utils($1)
		
	    virtual ${3:`substitute(expand('%:t:r'), '_driver$', '_if', '')`} vif;
		
	    extern function new(string name = "$1", uvm_component parent = null);
	    extern virtual function void build_phase(uvm_phase phase);
	    extern virtual task run_phase(uvm_phase phase);
	    extern virtual task drive_item($2 item);
		
	endclass: $1
		
	function $1::new(string name = "$1", uvm_component parent = null);
	    super.new(name, parent);
	endfunction: new
		
	function void $1::build_phase(uvm_phase phase);
	    super.build_phase(phase);
	    if (!uvm_config_db#(virtual $3)::get(this, "", "vif", vif))
	        \`uvm_fatal(get_name(), "Virtual interface not found!")
	endfunction: build_phase
		
	task $1::run_phase(uvm_phase phase);
	    forever begin
	        seq_item_port.get_next_item(req);
	        drive_item(req);
	        seq_item_port.item_done();
	    end
	endtask: run_phase
		
	task $1::drive_item($2 item);
	    // TODO: Implement protocol-specific driving
	    // Example:
	    // @(posedge vif.clk);
	    // vif.data <= item.data;
	    ${0}
	endtask: drive_item

snippet uvm_monitor
	class ${1:`expand('%:t:r')`} extends uvm_monitor;
	    \`uvm_component_utils($1)
		
	    uvm_analysis_port #(${2:`substitute(expand('%:t:r'), '_monitor$', '_item', '')`}) ap;
	    virtual ${3:`substitute(expand('%:t:r'), '_monitor$', '_if', '')`} vif;
		
	    extern function new(string name = "$1", uvm_component parent = null);
	    extern virtual function void build_phase(uvm_phase phase);
	    extern virtual task run_phase(uvm_phase phase);
	    extern virtual task collect_transaction(output $2 item);
		
	endclass: $1
		
	function $1::new(string name = "$1", uvm_component parent = null);
	    super.new(name, parent);
	endfunction: new
		
	function void $1::build_phase(uvm_phase phase);
	    super.build_phase(phase);
	    ap = new("ap", this);
	    if (!uvm_config_db#(virtual $3)::get(this, "", "vif", vif))
	        \`uvm_fatal(get_name(), "Virtual interface not found!")
	endfunction: build_phase
		
	task $1::run_phase(uvm_phase phase);
	    forever begin
	        $2 item;
	        collect_transaction(item);
	        \`uvm_info(get_name(), item.convert2string(), UVM_HIGH)
	        ap.write(item);
	    end
	endtask: run_phase
		
	task $1::collect_transaction(output $2 item);
	    item = $2::type_id::create("item");
	    // TODO: Implement protocol-specific monitoring
	    // Example:
	    // @(posedge vif.clk);
	    // if (vif.valid && vif.ready) begin
	    //   item.data = vif.data;
	    // end
	    ${0}
	endtask: collect_transaction

snippet uvm_sequencer
	class ${1:`expand('%:t:r')`} extends uvm_sequencer #(${2:`substitute(expand('%:t:r'), '_sequencer$', '_item', '')`});
	    \`uvm_component_utils($1)
		
	    extern function new(string name = "$1", uvm_component parent = null);
		
	endclass: $1
		
	function $1::new(string name = "$1", uvm_component parent = null);
	    super.new(name, parent);
	endfunction: new

snippet uvm_sequence
	class ${1:`expand('%:t:r')`} extends uvm_sequence #(${2:`substitute(expand('%:t:r'), '_\(seq\|sequence\)$', '_item', '')`});
	    \`uvm_object_utils($1)
		
	    // Sequence properties
	    rand int unsigned num_trans = ${3:10};
		
	    extern function new(string name = "$1");
	    extern virtual task body();
	    extern virtual task pre_body();
	    extern virtual task post_body();
		
	endclass: $1
		
	function $1::new(string name = "$1");
	    super.new(name);
	endfunction: new
		
	task $1::pre_body();
	    // Setup before sequence execution
	    \`uvm_info(get_type_name(), $sformatf("Starting sequence with %0d transactions", num_trans), UVM_MEDIUM)
	endtask: pre_body
		
	task $1::body();
	    repeat (num_trans) begin
	        \`uvm_do(req)
	    end
	endtask: body
		
	task $1::post_body();
	    // Cleanup after sequence execution
	    \`uvm_info(get_type_name(), "Sequence completed", UVM_MEDIUM)
	endtask: post_body

# moved: sequence_item to COMMONLY USED SNIPPETS
	// ============================================================================
	// UVM SEQUENCE ITEM - Transaction Object (UVM Cookbook 5.2)
	// ============================================================================
	class ${1:`expand('%:t:r')`} extends uvm_sequence_item;
	    \`uvm_object_utils($1)
		
	    // Transaction fields
	    rand bit [${2:7}:0] ${3:addr};
	    rand bit [${4:31}:0] ${5:data};
	    ${6}
		
	    // Constraints
	    constraint ${7:valid}_c {
	        ${8}
	    }
		
	    extern function new(string name = "$1");
	    extern function void do_copy(uvm_object rhs);
	    extern function bit do_compare(uvm_object rhs, uvm_comparer comparer);
	    extern function void do_print(uvm_printer printer);
	    extern function string convert2string();
		
	endclass: $1
		
	function $1::new(string name = "$1");
	    super.new(name);
	endfunction: new
		
	function void $1::do_copy(uvm_object rhs);
	    $1 rhs_;
	    if (!\$cast(rhs_, rhs))
	        \`uvm_fatal(get_type_name(), "Cast failed in do_copy")
	    super.do_copy(rhs);
	    this.$3 = rhs_.$3;
	    this.$5 = rhs_.$5;
	endfunction: do_copy
		
	function bit $1::do_compare(uvm_object rhs, uvm_comparer comparer);
	    $1 rhs_;
	    if (!\$cast(rhs_, rhs))
	        return 0;
	    return (super.do_compare(rhs, comparer) &&
	            (this.$3 == rhs_.$3) &&
	            (this.$5 == rhs_.$5));
	endfunction: do_compare
		
	function void $1::do_print(uvm_printer printer);
	    super.do_print(printer);
	    printer.print_field("$3", this.$3, $2+1);
	    printer.print_field("$5", this.$5, $4+1);
	endfunction: do_print
		
	function string $1::convert2string();
	    return $sformatf("$3=0x%0h, $5=0x%0h", $3, $5);
	endfunction: convert2string

snippet assert
	assert (${1:condition}) else \$error("${2:Assertion failed}");

snippet property
	property ${1:`expand('%:t:r')`};
	    @(posedge ${2:clk}) ${3:condition};
	endproperty: $1

snippet sequence
	sequence ${1:`expand('%:t:r')`};
	    ${2}
	endsequence: $1

snippet implication
	${1:antecedent} |-> ${2:consequent}

# =============================================================================
# FILE TEMPLATES AND HEADERS
# =============================================================================

snippet sv_header
	//==============================================================================
	// File        : ${1:`expand('%:t')`}
	// Project     : ${2:Project Name}
	// Module      : ${3:`expand('%:t:r')`}
	// Author      : ${4:$USER}
	// Created     : ${5:`strftime("%Y-%m-%d")`}
	// Modified    : ${6:`strftime("%Y-%m-%d")`}
	//==============================================================================
	// Description:
	//   ${7:Brief description}
	//==============================================================================
	
	${0}

snippet header_guard
	\`ifndef ${1:`toupper(substitute(expand('%:t:r'), '[^A-Z0-9]', '_', 'g'))`}_SVH
	\`define $1_SVH
	
	${0}
	
	\`endif // $1_SVH

snippet tb
	\`timescale 1ns/1ps
	
	module ${1:`expand('%:t:r')`};
	
	    localparam int PERIOD = ${2:10};
	    
	    logic ${3:clk};
	    logic ${4:rst_n};
	    ${5}
	
	    // Clock generation
	    initial begin
	        $3 = 0;
	        forever #(PERIOD/2) $3 = ~$3;
	    end
	
	    // Reset generation
	    initial begin
	        $4 = 0;
	        repeat(2) @(posedge $3);
	        $4 = 1;
	    end
	
	    // DUT instantiation
	    ${6:dut} u_dut (
	        .clk($3),
	        .rst_n($4)${7}
	    );
	
	    // Test stimulus
	    initial begin
	        @(posedge $4);
	        ${0}
	        #1000;
	        \$finish;
	    end
	
	    // Waveform dump
	    initial begin
	        \$dumpfile("${8:`expand('%:t:r')`}.vcd");
	        \$dumpvars(0, $1);
	    end
	
	endmodule: $1

# =============================================================================
# MODULE AND INTERFACE DEFINITIONS
# =============================================================================

snippet module
	module ${1:`expand('%:t:r')`} #(
	    parameter int ${2:WIDTH} = ${3:8}
	) (
	    input  logic ${4:clk},
	    input  logic ${5:rst_n},
	    ${6}
	);
	    ${0}
	endmodule: $1

snippet interface
	interface ${1:`expand('%:t:r')`} (
	    input logic clk,
	    input logic rst_n
	);
	    ${2}
	endinterface: $1

snippet modport
	modport ${1:`expand('%:t:r')`}_mp (
	    ${2:input clk}
	);

snippet package
	package ${1:`expand('%:t:r')`}_pkg;
	    ${2}
	endpackage: $1_pkg

snippet program
	program ${1:`expand('%:t:r')`};
	    ${2}
	endprogram: $1

# =============================================================================
# DATA TYPES
# =============================================================================

snippet logic
	logic ${1:[7:0]} ${2:signal}${3: = ${4:0}};

snippet wire
	wire ${1:[7:0]} ${2:signal};

snippet reg
	reg ${1:[7:0]} ${2:signal}${3: = ${4:0}};

snippet bit
	bit ${1:[7:0]} ${2:signal};

snippet byte
	byte ${1:variable};

snippet int
	int ${1:variable};

snippet parameter
	parameter ${1:int} ${2:`toupper(expand('%:t:r'))`} = ${3:value};

snippet localparam
	localparam ${1:int} ${2:`toupper(expand('%:t:r'))`} = ${3:value};

snippet typedef_struct
	typedef struct packed {
	    ${2}
	} ${1:`expand('%:t:r')`}_s;

snippet typedef_enum
	typedef enum logic ${1:[1:0]} {
	    ${2:IDLE}   = ${3:2'b00},
	    ${4:ACTIVE} = ${5:2'b01}
	} ${6:`expand('%:t:r')`}_e;

snippet typedef_union
	typedef union packed {
	    ${2}
	} ${1:`expand('%:t:r')`}_u;

snippet enum
	typedef enum ${1:logic} {
	    ${2:IDLE},
	    ${3:ACTIVE}
	} ${4:`expand('%:t:r')`}_e;

# =============================================================================
# ARRAYS
# =============================================================================

snippet dynamic_array
	${1:type} ${2:array}[];

snippet associative_array
	${1:type} ${2:array}[${3:key_type}];

snippet queue
	${1:type} ${2:queue}[$];

snippet packed_array
	${1:type} [${2:msb}:${3:lsb}] ${4:array};

snippet unpacked_array
	${1:type} ${2:array}[${3:size}];

snippet memory
	reg [${1:7}:0] ${2:memory} [0:${3:255}];

# =============================================================================
# PROCEDURAL BLOCKS
# =============================================================================

snippet initial
	initial begin
	    ${1}
	end

snippet always
	always @(${1:posedge clk}) begin
	    ${2}
	end

snippet always_ff
	always_ff @(posedge ${1:clk} or negedge ${2:rst_n}) begin
	    if (!$2)
	        ${3}
	    else
	        ${4}
	end

snippet always_comb
	always_comb begin
	    ${1}
	end

snippet always_latch
	always_latch begin
	    ${1}
	end

snippet final
	final begin
	    ${1}
	end

# =============================================================================
# CONTROL STRUCTURES
# =============================================================================

snippet if
	if (${1:condition}) begin
	    ${2}
	end

snippet ife
	if (${1:condition}) begin
	    ${2}
	end else begin
	    ${3}
	end

snippet case
	case (${1:expression})
	    ${2:value1}: begin
	        ${3}
	    end
	    default: begin
	        ${4}
	    end
	endcase

snippet casex
	casex (${1:expression})
	    ${2:value1}: ${3}
	    default: ${4}
	endcase

snippet casez
	casez (${1:expression})
	    ${2:value1}: ${3}
	    default: ${4}
	endcase

snippet unique
	unique case (${1:expression})
	    ${2:value}: ${3}
	    default: ${4}
	endcase

snippet priority
	priority case (${1:expression})
	    ${2:value}: ${3}
	    default: ${4}
	endcase

snippet ternary
	${1:condition} ? ${2:true} : ${3:false}

# =============================================================================
# LOOPS
# =============================================================================

snippet for
	for (${1:int i = 0}; ${2:i < n}; ${3:i++}) begin
	    ${4}
	end

snippet foreach
	foreach (${1:array}[${2:i}]) begin
	    ${3}
	end

snippet while
	while (${1:condition}) begin
	    ${2}
	end

snippet do
	do begin
	    ${2}
	end while (${1:condition});

snippet repeat
	repeat (${1:count}) begin
	    ${2}
	end

snippet forever
	forever begin
	    ${1}
	end

# =============================================================================
# FUNCTIONS AND TASKS
# =============================================================================

snippet function
	function ${1:void} ${2:`expand('%:t:r')`}(${3});
	    ${4}
	endfunction: $2

snippet task
	task ${1:`expand('%:t:r')`}(${2});
	    ${3}
	endtask: $1

snippet extern_function
	extern function ${1:return_type} ${2:`expand('%:t:r')`}(${3});

snippet extern_task
	extern task ${1:`expand('%:t:r')`}(${2});

# =============================================================================
# CLASSES
# =============================================================================

snippet class
	class ${1:`expand('%:t:r')`};
	    ${2}
	
	    function new(string name = "$1");
	        ${3}
	    endfunction: new
	
	endclass: $1

snippet class_param
	class ${1:`expand('%:t:r')`} #(
	    parameter int ${2:WIDTH} = ${3:8}
	);
	    ${4}
	
	    function new(string name = "$1");
	        ${5}
	    endfunction: new
	
	endclass: $1

snippet virtual_class
	virtual class ${1:`expand('%:t:r')`};
	    ${2}
	    pure virtual function ${3:void} ${4:method}();
	endclass: $1

snippet extends
	extends ${1:base_class}

snippet static
	static ${1:type} ${2:name};

snippet protected
	protected ${1:type} ${2:name};

snippet local
	local ${1:type} ${2:name};

# =============================================================================
# CONCURRENCY
# =============================================================================

snippet fork
	fork
	    begin
	        ${1}
	    end
	    begin
	        ${2}
	    end
	join

snippet fork_join_any
	fork
	    begin
	        ${1}
	    end
	join_any

snippet fork_join_none
	fork
	    begin
	        ${1}
	    end
	join_none

snippet wait
	wait (${1:condition});

snippet event
	event ${1:event_name};

snippet trigger
	-> ${1:event_name};

snippet mailbox
	mailbox #(${1:type}) ${2:mbx} = new(${3:bound});

snippet semaphore
	semaphore ${1:sem} = new(${2:count});

# =============================================================================
# RANDOMIZATION AND CONSTRAINTS
# =============================================================================

snippet randomize
	assert (${1:object}.randomize() with {
	    ${2:constraints}
	});

snippet constraint
	constraint ${1:name}_c {
	    ${2}
	}

snippet dist
	${1:variable} dist {
	    ${2:value1} := ${3:weight1},
	    ${4:value2} := ${5:weight2}
	};

snippet solve_before
	solve ${1:var1} before ${2:var2};

snippet soft
	soft ${1:variable} == ${2:value};

snippet inside
	${1:variable} inside {${2:range}};

snippet randcase
	randcase
	    ${1:weight1}: ${2:stmt1};
	    ${3:weight2}: ${4:stmt2};
	endcase

# =============================================================================
# COVERAGE
# =============================================================================

snippet covergroup
	covergroup ${1:`expand('%:t:r')`}_cg @(${2:posedge clk});
	    option.per_instance = 1;
	    ${3}
	endgroup: $1_cg

snippet coverpoint
	${1:signal}_cp: coverpoint ${2:signal} {
	    bins low  = {[0:${3:127}]};
	    bins high = {[${4:128}:255]};
	}

snippet cross
	${1:name}_cross: cross ${2:cp1}, ${3:cp2};

snippet bins
	bins ${1:name} = {${2:values}};

snippet ignore_bins
	ignore_bins ${1:name} = {${2:values}};

snippet illegal_bins
	illegal_bins ${1:name} = {${2:values}};

# =============================================================================
# ASSERTIONS
# =============================================================================

snippet assert
	assert (${1:condition}) else \$error("${2:Assertion failed}");

snippet property
	property ${1:`expand('%:t:r')};
	    @(posedge ${2:clk}) ${3:condition};
	endproperty: $1

snippet sequence
	sequence ${1:`expand('%:t:r')};
	    ${2}
	endsequence: $1

snippet assume
	assume property (${1:property_name});

snippet cover
	cover property (${1:property_name});

snippet sva
	property ${1:prop_name};
	    @(posedge ${2:clk}) disable iff (!${3:rst_n})
	    ${4:sequence};
	endproperty
	
	assert_$1: assert property ($1)
	    else \$error("$1 failed at %0t", \$time);

snippet implication
	${1:antecedent} |-> ${2:consequent}

snippet overlapping
	${1:antecedent} |=> ${2:consequent}

# =============================================================================
# GENERATE
# =============================================================================

snippet generate
	generate
	    for (genvar ${1:i} = 0; $1 < ${2:N}; $1++) begin : ${3:gen_block}
	        ${4}
	    end
	endgenerate

snippet generate_if
	generate
	    if (${1:condition}) begin : ${2:gen_label}
	        ${3}
	    end
	endgenerate

snippet genvar
	genvar ${1:i};

# =============================================================================
# INSTANTIATION
# =============================================================================

snippet inst
	${1:module_name} #(
	    .${2:PARAM}(${3:VALUE})
	) ${4:u_${1/([a-z]+).*/$1/}} (
	    .${5:clk}(${6:clk}),
	    .${7:rst_n}(${8:rst_n})${9}
	);

snippet port
	.${1:port}(${2:signal})${3:,}

snippet bind
	bind ${1:instance} ${2:module} ${3:bind_inst} (${4});

# =============================================================================
# CLOCKING
# =============================================================================

snippet clocking
	clocking ${1:`expand('%:t:r')`}_cb @(posedge ${2:clk});
	    default input #1step output #1ns;
	    ${3}
	endclocking: $1

# =============================================================================
# PREPROCESSOR DIRECTIVES
# =============================================================================

snippet define
	\`define ${1:`toupper(expand('%:t:r'))`} ${2:value}

snippet ifdef
	\`ifdef ${1:`toupper(expand('%:t:r'))`}
	    ${2}
	\`endif

snippet ifndef
	\`ifndef ${1:`toupper(expand('%:t:r'))`}
	    ${2}
	\`endif

snippet include
	\`include "${1:filename.svh}"

snippet timescale
	\`timescale ${1:1ns}/${2:1ps}

# =============================================================================
# SYSTEM TASKS
# =============================================================================

snippet display
	\$display("${1:message

snippet monitor
	\$monitor("Time=%0t: ${1:signal}=%0d", \$time, ${2:signal});

snippet finish
	\$finish;

snippet stop
	\$stop;

snippet readmemh
	\$readmemh("${1:file.hex}", ${2:memory});

snippet fopen
	integer ${1:fh};
	$1 = \$fopen("${2:file.txt}", "${3:w}");

snippet sformatf
	\$sformatf("${1:format}", ${2:args})

snippet urandom
	\$urandom()

snippet urandom_range
	\$urandom_range(${1:max}, ${2:min})

snippet cast
	\$cast(${1:dest}, ${2:source})

# =============================================================================
# FSM TEMPLATE
# =============================================================================

snippet fsm
	typedef enum logic [${1:1}:0] {
	    ${2:IDLE}   = ${3:2'b00},
	    ${4:ACTIVE} = ${5:2'b01},
	    ${6:DONE}   = ${7:2'b10}
	} ${8:state}_t;
	
	$8_t current_state, next_state;
	
	always_ff @(posedge ${9:clk} or negedge ${10:rst_n}) begin
	    if (!$10)
	        current_state <= $2;
	    else
	        current_state <= next_state;
	end
	
	always_comb begin
	    next_state = current_state;
	    case (current_state)
	        $2:   ${11}
	        $4:   ${12}
	        $6:   ${13}
	        default: next_state = $2;
	    endcase
	end

# =============================================================================
# COMMON PATTERNS
# =============================================================================

snippet fifo
	logic [${1:DEPTH_W}-1:0] wr_ptr, rd_ptr;
	logic [${2:DATA_W}-1:0] mem [2**$1];
	logic empty, full;
	
	assign empty = (wr_ptr == rd_ptr);
	assign full  = (wr_ptr + 1 == rd_ptr);

snippet handshake
	logic ${1:valid}, ${2:ready};
	
	always_ff @(posedge ${3:clk} or negedge ${4:rst_n}) begin
	    if (!$4)
	        $1 <= 1'b0;
	    else if ($1 && $2)
	        $1 <= 1'b0;
	    else if (${5:condition})
	        $1 <= 1'b1;
	end

snippet assign
	assign ${1:target} = ${2:expression};

# =============================================================================
# UVM COMPONENTS
# =============================================================================

snippet component_param sequence
	class ${1:`expand('%:t:r')`} #(
	    parameter int ${2:DATA_WIDTH} = ${3:32}
	) extends uvm_sequence #(${4:`substitute(expand('%:t:r'), '_\(seq\|sequence\)$', '_item', '')`}#($2));
	    `uvm_object_param_utils($1#($2))
	
	    typedef $4#($2) item_t;
	    rand int unsigned num_trans = ${5:10};
	
	    extern function new(string name = "$1");
	    extern virtual task body();
	
	endclass: $1
	
	function $1#($2)::new(string name = "$1");
	    super.new(name);
	endfunction: new
	
	task $1#($2)::body();
	    repeat (num_trans) begin
	        `uvm_do(req)
	    end
	endtask: body

snippet sequence_item
	class ${1:`expand('%:t:r')`} extends uvm_sequence_item;
	    `uvm_object_utils($1)
	
	    // Transaction fields
	    rand bit [${2:7}:0] ${3:addr};
	    rand bit [${4:31}:0] ${5:data};
	    ${6}
	
	    // Constraints
	    constraint ${7:valid}_c {
	        ${8}
	    }
	
	    extern function new(string name = "$1");
	    extern function void do_copy(uvm_object rhs);
	    extern function bit do_compare(uvm_object rhs, uvm_comparer comparer);
	    extern function void do_print(uvm_printer printer);
	    extern function string convert2string();
	
	endclass: $1
	
	function $1::new(string name = "$1");
	    super.new(name);
	endfunction: new
	
	function void $1::do_copy(uvm_object rhs);
	    $1 rhs_;
	    if (!$cast(rhs_, rhs))
	        `uvm_fatal(get_type_name(), "Cast failed in do_copy")
	    super.do_copy(rhs);
	    this.$3 = rhs_.$3;
	    this.$5 = rhs_.$5;
	endfunction: do_copy
	
	function bit $1::do_compare(uvm_object rhs, uvm_comparer comparer);
	    $1 rhs_;
	    if (!$cast(rhs_, rhs))
	        return 0;
	    return (super.do_compare(rhs, comparer) &&
	            (this.$3 == rhs_.$3) &&
	            (this.$5 == rhs_.$5));
	endfunction: do_compare
	
	function void $1::do_print(uvm_printer printer);
	    super.do_print(printer);
	    printer.print_field("$3", this.$3, $2+1);
	    printer.print_field("$5", this.$5, $4+1);
	endfunction: do_print
	
	function string $1::convert2string();
	    return $sformatf("$3=0x%0h, $5=0x%0h", $3, $5);
	endfunction: convert2string

# =============================================================================
# SYSTEMVERILOG ASSERTIONS (SVA) - COMPREHENSIVE
# =============================================================================

snippet sva_property
	// ============================================================================
	// SVA PROPERTY - Assertion Property (IEEE 1800-2017 Chapter 16)
	// ============================================================================
	// Purpose: Define temporal property for verification
	//
	// Property Structure:
	//   property name;
	//     @(posedge clk) disable iff (reset)
	//     antecedent |-> consequent;
	//   endproperty
	//
	// Implication Operators:
	//   |->  Overlapping (consequent checked same cycle)
	//   |=>  Non-overlapping (consequent checked next cycle)
	//
	// Sequence Operators:
	//   ##n  - Delay by n cycles
	//   ##[m:n] - Delay between m and n cycles
	//   [*n] - Repeat exactly n times
	//   [*m:n] - Repeat between m and n times
	//   [->n] - Goto repetition (non-consecutive)
	//   [=n]  - Non-consecutive repetition
	//
	// Example:
	//   property req_ack;
	//     @(posedge clk) disable iff (rst)
	//     req |-> ##[1:3] ack;
	//   endproperty
	// ============================================================================
	property ${1:prop_name};
	    @(posedge ${2:clk}) disable iff (${3:!rst_n})
	    ${4:antecedent} |-> ${5:consequent};
	endproperty: $1
	
	${6:assert_}$1: assert property ($1)
	    else `uvm_error("ASSERT", $sformatf("$1 failed at %0t", $time))

snippet sva_sequence
	sequence ${1:seq_name};
	    ${2:expression};
	endsequence: $1

snippet sva_implication
	property ${1:overlap_prop};
	    @(posedge ${2:clk}) disable iff (${3:!rst_n})
	    ${4:req} |-> ${5:grant};  // If req this cycle, grant must be true this cycle
	endproperty
	
	property ${6:nonoverlap_prop};
	    @(posedge $2) disable iff ($3)
	    $4 |=> $5;  // If req this cycle, grant must be true next cycle
	endproperty

snippet sva_delay
	// Fixed Delay: ##n
	property ${1:fixed_delay};
	    @(posedge ${2:clk})
	    ${3:req} |-> ##${4:2} ${5:ack};  // ack exactly 2 cycles after req
	endproperty
	
	// Range Delay: ##[m:n]
	property ${6:range_delay};
	    @(posedge $2)
	    $3 |-> ##[${7:1}:${8:5}] $5;  // ack within 1-5 cycles after req
	endproperty
	
	// Unbounded Delay: ##[1:$]
	property ${9:unbounded_delay};
	    @(posedge $2)
	    $3 |-> ##[1:$] $5;  // ack eventually after req
	endproperty

snippet sva_repetition
	// Consecutive Repetition: [*n]
	property ${1:consecutive_rep};
	    @(posedge ${2:clk})
	    ${3:busy}[*${4:3}] ##1 ${5:done};  // busy for exactly 3 cycles, then done
	endproperty
	
	// Range Repetition: [*m:n]
	property ${6:range_rep};
	    @(posedge $2)
	    $3[*${7:2}:${8:5}] ##1 $5;  // busy for 2-5 cycles, then done
	endproperty
	
	// Goto Repetition: [->n]
	property ${9:goto_rep};
	    @(posedge $2)
	    ${10:valid}[->3] ##1 ${11:complete};  // valid high 3 times (non-consecutive), then complete
	endproperty
	
	// Non-consecutive Repetition: [=n]
	property ${12:noncons_rep};
	    @(posedge $2)
	    $10[=3];  // valid high 3 times (may be non-consecutive)
	endproperty

snippet sva_throughout
	property ${1:throughout_prop};
	    @(posedge ${2:clk})
	    ${3:enable} throughout (${4:req} ##[1:5] ${5:ack});
	    // enable must remain high from req until ack
	endproperty

snippet sva_advanced
	
	// 1. Request-Acknowledge with Timeout
	property ${1:req_ack_timeout};
	    @(posedge ${2:clk}) disable iff (${3:!rst_n})
	    ${4:req} |-> ##[1:${5:10}] ${6:ack};
	endproperty
	
	// 2. Mutual Exclusion
	property ${7:mutex};
	    @(posedge $2) disable iff ($3)
	    ${8:sig_a} |-> !${9:sig_b};
	endproperty
	
	// 3. FIFO Full/Empty Relationship
	property ${10:fifo_full_empty};
	    @(posedge $2) disable iff ($3)
	    !(${11:full} && ${12:empty});
	endproperty
	
	// 4. Handshake Protocol
	property ${13:handshake};
	    @(posedge $2) disable iff ($3)
	    ${14:valid} && ${15:ready} |=> !${16:valid} || ${17:new_data};
	endproperty
	
	// 5. One-Hot Encoding
	property ${18:onehot};
	    @(posedge $2)
	    $onehot(${19:state});
	endproperty

snippet sva_cover
	property ${1:cover_prop};
	    @(posedge ${2:clk})
	    ${3:condition};
	endproperty
	
	cover_$1: cover property ($1)
	    `uvm_info("COVER", $sformatf("$1 covered at %0t", $time), UVM_MEDIUM)

snippet sva_assume
	property ${1:assume_prop};
	    @(posedge ${2:clk})
	    ${3:input_constraint};
	endproperty
	
	assume_$1: assume property ($1);

snippet sva_concurrent
	${1:assert_name}: assert property (
	    @(posedge ${2:clk}) disable iff (${3:!rst_n})
	    ${4:property_expression}
	) else `uvm_error("ASSERT", "$1 failed");

snippet sva_immediate
	assert (${1:condition}) else `uvm_error("ASSERT", "${2:Assertion failed}");

snippet sva_system
	// $rose - Detects 0->1 transition
	property ${1:rose_detect};
	    @(posedge ${2:clk})
	    $rose(${3:signal}) |-> ${4:action};
	endproperty
	
	// $fell - Detects 1->0 transition
	property ${5:fell_detect};
	    @(posedge $2)
	    $fell($3) |-> $4;
	endproperty
	
	// $stable - Signal unchanged
	property ${6:stable_check};
	    @(posedge $2)
	    ${7:hold} |-> $stable($3);
	endproperty
	
	// $past - Previous value
	property ${8:past_check};
	    @(posedge $2)
	    ${9:valid} |-> ${10:data} == $past(${11:prev_data});
	endproperty
	
	// $onehot - Exactly one bit high
	property ${12:onehot_check};
	    @(posedge $2)
	    $onehot(${13:state_vector});
	endproperty
	
	// $onehot0 - At most one bit high
	property ${14:onehot0_check};
	    @(posedge $2)
	    $onehot0($13);
	endproperty
	
	// $isunknown - Check for X/Z
	property ${15:unknown_check};
	    @(posedge $2)
	    !$isunknown($3);
	endproperty

snippet sva_fifo
	
	// 1. No write when full
	property ${1:no_write_when_full};
	    @(posedge ${2:clk}) disable iff (${3:!rst_n})
	    ${4:full} |-> !${5:wr_en};
	endproperty
	assert_$1: assert property ($1);
	
	// 2. No read when empty
	property ${6:no_read_when_empty};
	    @(posedge $2) disable iff ($3)
	    ${7:empty} |-> !${8:rd_en};
	endproperty
	assert_$6: assert property ($6);
	
	// 3. Write increments count (when not full)
	property ${9:write_inc_count};
	    @(posedge $2) disable iff ($3)
	    $5 && !$4 |=> ${10:count} == $past($10) + 1;
	endproperty
	assert_$9: assert property ($9);
	
	// 4. Read decrements count (when not empty)
	property ${11:read_dec_count};
	    @(posedge $2) disable iff ($3)
	    $8 && !$7 |=> $10 == $past($10) - 1;
	endproperty
	assert_$11: assert property ($11);
	
	// 5. Full and empty are mutually exclusive
	property ${12:full_empty_mutex};
	    @(posedge $2)
	    !($4 && $7);
	endproperty
	assert_$12: assert property ($12);

snippet sva_axi
	
	// 1. Valid-Ready Handshake (AXI Rule)
	property ${1:axi_valid_stable};
	    @(posedge ${2:clk}) disable iff (${3:!rst_n})
	    ${4:valid} && !${5:ready} |=> $stable($4) && $stable(${6:data});
	endproperty
	assert_$1: assert property ($1)
	    else `uvm_error("AXI", "VALID/data must remain stable until READY");
	
	// 2. BVALID follows WLAST and WREADY
	property ${7:axi_bvalid_after_wlast};
	    @(posedge $2) disable iff ($3)
	    ${8:wlast} && ${9:wready} |-> ##[1:${10:16}] ${11:bvalid};
	endproperty
	assert_$7: assert property ($7);
	
	// 3. RVALID must not be dependent on RREADY
	property ${12:axi_rvalid_independent};
	    @(posedge $2) disable iff ($3)
	    ${13:rvalid} |-> ${13:rvalid} throughout (##[0:$] ${14:rready});
	endproperty
	assert_$12: assert property ($12);

# =============================================================================
# MACROS AND PREPROCESSOR (IEEE 1800-2012 Section 22)
# =============================================================================

snippet macro_define
	\`define ${1:MACRO_NAME}(${2:args}) \\
	    ${3:macro body}

snippet macro_stringify
	\`define ${1:TO_STRING}(${2:x}) \`"${2}\`"

snippet macro_concat
	\`define ${1:CONCAT}(${2:a}, ${3:b}) ${2}\`\`${3}

snippet macro_ifdef_block
	\`ifdef ${1:MACRO_NAME}
	    ${2:code when defined}
	\`else
	    ${3:code when not defined}
	\`endif

snippet macro_ifndef_block
	\`ifndef ${1:MACRO_NAME}
	    ${2:code when not defined}
	\`else
	    ${3:code when defined}
	\`endif

snippet macro_undef
	\`undef ${1:MACRO_NAME}

snippet macro_line
	\`line ${1:line_number} "${2:filename}" ${3:level}

snippet macro_default
	\`default_nettype ${1:wire}

snippet macro_resetall
	\`resetall

snippet macro_celldefine
	\`celldefine
	${1}
	\`endcelldefine

snippet macro_pragma
	\`pragma ${1:pragma_name} ${2:pragma_value}

snippet macro_begin_keywords
	\`begin_keywords "${1:1800-2012}"
	${2}
	\`end_keywords

# =============================================================================
# COMMON UVM MACROS
# =============================================================================

snippet uvm_info_macro
	\`uvm_info("${1:ID}", $sformatf("${2:Message: %s}", ${3:arg}), ${4:UVM_MEDIUM})

snippet uvm_warning_macro
	\`uvm_warning("${1:ID}", $sformatf("${2:Message: %s}", ${3:arg}))

snippet uvm_error_macro
	\`uvm_error("${1:ID}", $sformatf("${2:Message: %s}", ${3:arg}))

snippet uvm_fatal_macro
	\`uvm_fatal("${1:ID}", $sformatf("${2:Message: %s}", ${3:arg}))

snippet uvm_do_macro
	\`uvm_do(${1:sequence_item})

snippet uvm_do_with_macro
	\`uvm_do_with(${1:sequence_item}, {
	    ${2:constraints}
	})

snippet uvm_create_macro
	\`uvm_create(${1:sequence_item})

snippet uvm_send_macro
	\`uvm_send(${1:sequence_item})

snippet uvm_rand_send_macro
	\`uvm_rand_send(${1:sequence_item})

snippet uvm_rand_send_with_macro
	\`uvm_rand_send_with(${1:sequence_item}, {
	    ${2:constraints}
	})

snippet uvm_field_int
	\`uvm_field_int(${1:field_name}, ${2:UVM_DEFAULT})

snippet uvm_field_object
	\`uvm_field_object(${1:field_name}, ${2:UVM_DEFAULT})

snippet uvm_field_string
	\`uvm_field_string(${1:field_name}, ${2:UVM_DEFAULT})

snippet uvm_field_enum
	\`uvm_field_enum(${1:enum_type}, ${2:field_name}, ${3:UVM_DEFAULT})

snippet uvm_field_array_int
	\`uvm_field_array_int(${1:field_name}, ${2:UVM_DEFAULT})

snippet uvm_field_sarray_int
	\`uvm_field_sarray_int(${1:field_name}, ${2:UVM_DEFAULT})

snippet uvm_field_queue
	\`uvm_field_queue_${1:int}(${2:field_name}, ${3:UVM_DEFAULT})

snippet uvm_field_aa
	\`uvm_field_aa_${1:int}_${2:string}(${3:field_name}, ${4:UVM_DEFAULT})

# =============================================================================
# COMMON UTILITY MACROS
# =============================================================================

snippet macro_min
	\`define MIN(a, b) (((a) < (b)) ? (a) : (b))

snippet macro_max
	\`define MAX(a, b) (((a) > (b)) ? (a) : (b))

snippet macro_abs
	\`define ABS(x) (((x) < 0) ? -(x) : (x))

snippet macro_clamp
	\`define CLAMP(x, min, max) (((x) < (min)) ? (min) : (((x) > (max)) ? (max) : (x)))

snippet macro_swap
	\`define SWAP(a, b, tmp) \\
	    tmp = a; \\
	    a = b; \\
	    b = tmp;

snippet macro_bit_width
	\`define BIT_WIDTH(x) ($clog2(x))

snippet macro_is_power_of_2
	\`define IS_POWER_OF_2(x) (((x) != 0) && (((x) & ((x) - 1)) == 0))

snippet macro_align_up
	\`define ALIGN_UP(x, align) ((((x) + (align) - 1) / (align)) * (align))

snippet macro_div_round_up
	\`define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))

# =============================================================================
# VERIFICATION MACROS
# =============================================================================

snippet macro_check_fatal
	\`define CHECK_FATAL(cond, msg) \\
	    if (!(cond)) begin \\
	        \$fatal(1, msg); \\
	    end

snippet macro_check_error
	\`define CHECK_ERROR(cond, msg) \\
	    if (!(cond)) begin \\
	        \$error(msg); \\
	    end

snippet macro_check_warning
	\`define CHECK_WARNING(cond, msg) \\
	    if (!(cond)) begin \\
	        \$warning(msg); \\
	    end

snippet macro_assert
	\`define ASSERT(cond) \\
	    assert(cond) else \$error("Assertion failed: \`"cond\`" at %m")

snippet macro_cover
	\`define COVER(name, cond) \\
	    cover property (@(posedge clk) cond) \\
	        \$display("Coverage: name hit at %t", \$time);

# =============================================================================
# DEBUG MACROS
# =============================================================================

snippet macro_debug
	\`ifdef DEBUG
	    \`define DEBUG_PRINT(msg) \$display("[DEBUG] %t: msg", \$time)
	\`else
	    \`define DEBUG_PRINT(msg)
	\`endif

snippet macro_verbose
	\`ifdef VERBOSE
	    \`define VERBOSE_PRINT(level, msg) \\
	        if (verbose_level >= level) \$display("[VERBOSE] msg")
	\`else
	    \`define VERBOSE_PRINT(level, msg)
	\`endif

snippet macro_trace
	\`define TRACE(msg) \$display("[TRACE] %t %m: msg", \$time)

snippet macro_dump_vars
	\`define DUMP_VARS(var) \\
	    \$display("[DUMP] %t %m: \`"var\`" = %0d", \$time, var)

# =============================================================================
# REGISTER ACCESS MACROS
# =============================================================================

snippet macro_reg_write
	\`define REG_WRITE(addr, data) \\
	    @(posedge clk); \\
	    reg_addr = addr; \\
	    reg_wdata = data; \\
	    reg_wr_en = 1'b1; \\
	    @(posedge clk); \\
	    reg_wr_en = 1'b0;

snippet macro_reg_read
	\`define REG_READ(addr, data) \\
	    @(posedge clk); \\
	    reg_addr = addr; \\
	    reg_rd_en = 1'b1; \\
	    @(posedge clk); \\
	    data = reg_rdata; \\
	    reg_rd_en = 1'b0;

snippet macro_reg_field
	\`define REG_FIELD(reg, msb, lsb) reg[msb:lsb]

snippet macro_reg_bit
	\`define REG_BIT(reg, bit) reg[bit]

# =============================================================================
# TIMING MACROS
# =============================================================================

snippet macro_wait_clks
	\`define WAIT_CLKS(n) \\
	    repeat(n) @(posedge clk);

snippet macro_wait_ns
	\`define WAIT_NS(ns) \\
	    #(ns * 1ns);

snippet macro_wait_until
	\`define WAIT_UNTIL(cond) \\
	    wait(cond);

snippet macro_wait_clk_edge
	\`define WAIT_CLK_EDGE \\
	    @(posedge clk);

# =============================================================================
# ARRAY/MEMORY MACROS
# =============================================================================

snippet macro_array_sum
	\`define ARRAY_SUM(arr, size) \\
	    function int; \\
	        int sum = 0; \\
	        for (int i = 0; i < size; i++) \\
	            sum += arr[i]; \\
	        return sum; \\
	    endfunction

snippet macro_array_fill
	\`define ARRAY_FILL(arr, size, val) \\
	    for (int i = 0; i < size; i++) \\
	        arr[i] = val;

snippet macro_array_copy
	\`define ARRAY_COPY(dst, src, size) \\
	    for (int i = 0; i < size; i++) \\
	        dst[i] = src[i];

# =============================================================================
# CONDITIONAL COMPILATION MACROS
# =============================================================================

snippet macro_synthesis
	\`ifdef SYNTHESIS
	    ${1:// Synthesis code}
	\`else
	    ${2:// Simulation code}
	\`endif

snippet macro_formal
	\`ifdef FORMAL
	    ${1:// Formal verification code}
	\`endif

snippet macro_coverage
	\`ifdef COVERAGE
	    ${1:// Coverage code}
	\`endif

snippet macro_simulation
	\`ifndef SYNTHESIS
	    ${1:// Simulation-only code}
	\`endif

# =============================================================================
# PARAMETERIZED MACROS (Advanced)
# =============================================================================

snippet macro_gen_comparator
	\`define GEN_COMPARATOR(name, width) \\
	module name ( \\
	    input  logic [width-1:0] a, \\
	    input  logic [width-1:0] b, \\
	    output logic             eq, \\
	    output logic             gt, \\
	    output logic             lt  \\
	); \\
	    assign eq = (a == b); \\
	    assign gt = (a > b); \\
	    assign lt = (a < b); \\
	endmodule

snippet macro_gen_register
	\`define GEN_REGISTER(name, width, reset_val) \\
	always_ff @(posedge clk or negedge rst_n) begin \\
	    if (!rst_n) \\
	        name <= reset_val; \\
	    else if (name``_en) \\
	        name <= name``_next; \\
	end

snippet macro_gen_fifo
	\`define GEN_FIFO(name, width, depth) \\
	logic [width-1:0] name``_mem [depth]; \\
	logic [\$clog2(depth)-1:0] name``_wr_ptr, name``_rd_ptr; \\
	logic name``_full, name``_empty;

# =============================================================================
# PROTOCOL-SPECIFIC MACROS
# =============================================================================

snippet macro_axi_handshake
	\`define AXI_HANDSHAKE(valid, ready) \\
	    (valid && ready)

snippet macro_axi_wait
	\`define AXI_WAIT_HANDSHAKE(valid, ready) \\
	    do begin \\
	        @(posedge clk); \\
	    end while (!(valid && ready));

snippet macro_apb_write
	\`define APB_WRITE(addr, data) \\
	    @(posedge clk); \\
	    paddr = addr; \\
	    pwdata = data; \\
	    pwrite = 1'b1; \\
	    psel = 1'b1; \\
	    @(posedge clk); \\
	    penable = 1'b1; \\
	    @(posedge clk); \\
	    psel = 1'b0; \\
	    penable = 1'b0;

snippet macro_apb_read
	\`define APB_READ(addr, data) \\
	    @(posedge clk); \\
	    paddr = addr; \\
	    pwrite = 1'b0; \\
	    psel = 1'b1; \\
	    @(posedge clk); \\
	    penable = 1'b1; \\
	    @(posedge clk); \\
	    data = prdata; \\
	    psel = 1'b0; \\
	    penable = 1'b0;

# =============================================================================
# STRING MANIPULATION MACROS
# =============================================================================

snippet macro_str_concat
	\`define STR_CONCAT(a, b) {a, b}

snippet macro_str_format
	\`define STR_FORMAT(fmt, args) \\
	    \$sformatf(fmt, args)

snippet macro_to_hex
	\`define TO_HEX(val, width) \\
	    \$sformatf("0x%0h", val)

snippet macro_to_bin
	\`define TO_BIN(val, width) \\
	    \$sformatf("%0b", val)

# =============================================================================
# FILE I/O MACROS
# =============================================================================

snippet macro_file_open
	\`define FILE_OPEN(handle, filename, mode) \\
	    handle = \$fopen(filename, mode); \\
	    if (!handle) \\
	        \$fatal(1, "Failed to open file: filename");

snippet macro_file_write
	\`define FILE_WRITE(handle, fmt, args) \\
	    \$fdisplay(handle, fmt, args);

snippet macro_file_close
	\`define FILE_CLOSE(handle) \\
	    \$fclose(handle);

# =============================================================================
# RANDOM MACROS
# =============================================================================

snippet macro_rand_range
	\`define RAND_RANGE(min, max) \\
	    (\$urandom_range(max, min))

snippet macro_rand_bool
	\`define RAND_BOOL \\
	    (\$urandom() & 1)

snippet macro_rand_choice
	\`define RAND_CHOICE(arr, size) \\
	    arr[\$urandom_range(size-1, 0)]

# =============================================================================
# PERFORMANCE MEASUREMENT MACROS
# =============================================================================

snippet macro_perf_start
	\`define PERF_START(name) \\
	    realtime name``_start_time = \$realtime;

snippet macro_perf_end
	\`define PERF_END(name) \\
	    \$display("[PERF] name: %.2f ns", \$realtime - name``_start_time);

snippet macro_cycle_count
	\`define CYCLE_COUNT_START(name) \\
	    int name``_cycle_count = 0;

snippet macro_cycle_count_inc
	\`define CYCLE_COUNT_INC(name) \\
	    name``_cycle_count++;

snippet macro_cycle_count_report
	\`define CYCLE_COUNT_REPORT(name) \\
	    \$display("[CYCLES] name: %0d cycles", name``_cycle_count);

# =============================================================================
# ADDITIONAL SYSTEMVERILOG CONSTRUCTS (IEEE 1800-2012)
# =============================================================================

snippet checker
	checker ${1:checker_name} (
	    ${2:input logic clk},
	    ${3:input logic rst_n}
	);
	    ${4:// Assertions}
	    ${0}
	endchecker: $1

snippet let
	let ${1:name} = ${2:expression};

snippet expect
	expect (${1:property_name}) else ${2:action};

snippet restrict
	restrict property (${1:property_name});

snippet alias
	alias ${1:new_name} = ${2:existing_name};

snippet nettype
	nettype ${1:data_type} ${2:nettype_name} with ${3:resolution_function};

# =============================================================================
# INTERFACE AND MODPORT ADVANCED
# =============================================================================

snippet interface_class
	interface class ${1:interface_name};
	    pure virtual function ${2:void} ${3:method}(${4});
	endclass: $1

snippet implements
	implements ${1:interface_class_name}

snippet modport_clocking
	modport ${1:name} (
	    clocking ${2:cb},
	    ${3:input reset}
	);

snippet interface_param
	interface ${1:`expand('%:t:r')`} #(
	    parameter int ${2:WIDTH} = ${3:8}
	) (
	    input logic clk,
	    input logic rst_n
	);
	    ${4}
	endinterface: $1

# =============================================================================
# ADVANCED CLASS FEATURES
# =============================================================================

snippet extern_class
	extern class ${1:class_name};

snippet constraint_mode
	${1:constraint_name}.constraint_mode(${2:0});

snippet rand_mode
	${1:variable}.rand_mode(${2:0});

snippet this
	this.${1:member}

snippet super
	super.${1:method}(${2});

snippet new_array
	${1:array} = new[${2:size}];

snippet new_copy
	${1:object} = new ${2:original};

# =============================================================================
# PACKAGE IMPORT AND EXPORT
# =============================================================================

snippet import_pkg
	import ${1:package_name}::${2:*};

snippet export_pkg
	export ${1:package_name}::${2:*};

snippet import_item
	import ${1:package_name}::${2:item_name};

# =============================================================================
# VIRTUAL INTERFACES
# =============================================================================

snippet virtual_interface
	virtual ${1:interface_name} ${2:vif};

snippet virtual_interface_param
	virtual ${1:interface_name}#(${2:params}) ${3:vif};

# =============================================================================
# DPI (Direct Programming Interface)
# =============================================================================

snippet dpi_import
	import "DPI-C" function ${1:return_type} ${2:function_name}(${3:args});

snippet dpi_export
	export "DPI-C" function ${1:function_name};

snippet dpi_context
	import "DPI-C" context function ${1:return_type} ${2:function_name}(${3:args});

snippet dpi_pure
	import "DPI-C" pure function ${1:return_type} ${2:function_name}(${3:args});

# =============================================================================
# PROGRAM BLOCKS (Advanced)
# =============================================================================

snippet program_clocking
	program ${1:`expand('%:t:r')`} (
	    ${2:interface_name}.${3:modport} ${4:port}
	);
	    clocking ${5:cb} @(posedge ${4}.clk);
	        ${6}
	    endclocking
	    
	    initial begin
	        ${0}
	    end
	endprogram: $1

# =============================================================================
# CONFIG AND BIND
# =============================================================================

snippet config
	config ${1:config_name};
	    design ${2:top_module};
	    ${3}
	endconfig: $1

snippet cell_config
	cell ${1:instance_path} use ${2:library}.${3:cell};

snippet instance_config
	instance ${1:instance_path} use ${2:configuration};

# =============================================================================
# SPECIFY BLOCKS (Timing)
# =============================================================================

snippet specify
	specify
	    specparam ${1:tPD} = ${2:10};
	    (${3:input} => ${4:output}) = $1;
	endspecify

snippet setuphold
	\$setuphold(posedge ${1:clk}, ${2:data}, ${3:setup_time}, ${4:hold_time});

snippet width_check
	\$width(posedge ${1:signal}, ${2:min_width});

snippet period_check
	\$period(posedge ${1:clk}, ${2:min_period});

# =============================================================================
# UNIQUE, PRIORITY, UNIQUE0
# =============================================================================

snippet unique_if
	unique if (${1:condition}) begin
	    ${2}
	end else if (${3:condition}) begin
	    ${4}
	end

snippet priority_if
	priority if (${1:condition}) begin
	    ${2}
	end else if (${3:condition}) begin
	    ${4}
	end

snippet unique0_case
	unique0 case (${1:expression})
	    ${2:value}: ${3}
	    default: ${4}
	endcase

# =============================================================================
# STREAMING OPERATORS
# =============================================================================

snippet stream_pack
	{<<{${1:data}}}

snippet stream_unpack
	{>>{${1:data}}}

snippet stream_slice
	{<<${1:8}{${2:data}}}

# =============================================================================
# ARRAY METHODS
# =============================================================================

snippet array_size
	${1:array}.size()

snippet array_delete
	${1:array}.delete(${2:index});

snippet array_exists
	${1:array}.exists(${2:index})

snippet array_first
	${1:array}.first(${2:index})

snippet array_last
	${1:array}.last(${2:index})

snippet array_next
	${1:array}.next(${2:index})

snippet array_prev
	${1:array}.prev(${2:index})

snippet array_find
	${1:array}.find(${2:item}) with (${3:item} == ${4:value})

snippet array_find_index
	${1:array}.find_index with (${2:item} == ${3:value})

snippet array_find_first
	${1:array}.find_first with (${2:item} > ${3:value})

snippet array_min
	${1:array}.min()

snippet array_max
	${1:array}.max()

snippet array_sum
	${1:array}.sum()

snippet array_product
	${1:array}.product()

snippet array_and
	${1:array}.and()

snippet array_or
	${1:array}.or()

snippet array_xor
	${1:array}.xor()

snippet array_unique
	${1:array}.unique()

snippet array_sort
	${1:array}.sort()

snippet array_rsort
	${1:array}.rsort()

snippet array_reverse
	${1:array}.reverse()

snippet array_shuffle
	${1:array}.shuffle()

# =============================================================================
# STRING METHODS
# =============================================================================

snippet string_len
	${1:str}.len()

snippet string_getc
	${1:str}.getc(${2:index})

snippet string_putc
	${1:str}.putc(${2:index}, ${3:char})

snippet string_toupper
	${1:str}.toupper()

snippet string_tolower
	${1:str}.tolower()

snippet string_compare
	${1:str}.compare(${2:str2})

snippet string_icompare
	${1:str}.icompare(${2:str2})

snippet string_substr
	${1:str}.substr(${2:start}, ${3:end})

snippet string_atoi
	${1:str}.atoi()

snippet string_atohex
	${1:str}.atohex()

snippet string_atooct
	${1:str}.atooct()

snippet string_atobin
	${1:str}.atobin()

snippet string_atoreal
	${1:str}.atoreal()

snippet string_itoa
	${1:str}.itoa(${2:value})

snippet string_hextoa
	${1:str}.hextoa(${2:value})

snippet string_octtoa
	${1:str}.octtoa(${2:value})

snippet string_bintoa
	${1:str}.bintoa(${2:value})

snippet string_realtoa
	${1:str}.realtoa(${2:value})

# =============================================================================
# PROCESS CONTROL
# =============================================================================

snippet process_self
	process::self()

snippet process_status
	${1:proc}.status()

snippet process_kill
	${1:proc}.kill()

snippet process_await
	${1:proc}.await()

snippet process_suspend
	${1:proc}.suspend()

snippet process_resume
	${1:proc}.resume()

# =============================================================================
# REFINEMENT (IEEE 1800-2012)
# =============================================================================

snippet global_clocking
	global clocking ${1:cb} @(posedge ${2:clk});
	    ${3}
	endclocking

snippet default_clocking
	default clocking ${1:cb};

snippet default_disable
	default disable iff ${1:reset};

# =============================================================================
# COVERAGE OPTIONS
# =============================================================================

snippet covergroup_option
	option.name = "${1:name}";
	option.weight = ${2:1};
	option.goal = ${3:100};
	option.comment = "${4:comment}";
	option.at_least = ${5:1};
	option.auto_bin_max = ${6:64};
	option.per_instance = ${7:0};
	option.get_inst_coverage = ${8:0};

snippet coverpoint_option
	option.weight = ${1:1};
	option.goal = ${2:100};
	option.comment = "${3:comment}";
	option.at_least = ${4:1};
	option.auto_bin_max = ${5:64};

# =============================================================================
# WILDCARD BINS
# =============================================================================

snippet bins_wildcard
	wildcard bins ${1:name} = {${2:4'b10??}};

snippet bins_transition
	bins ${1:name} = (${2:val1} => ${3:val2} => ${4:val3});

snippet bins_sequence
	bins ${1:name} = (${2:val1}[*${3:2}] => ${4:val2});

# =============================================================================
# RANDSEQUENCE
# =============================================================================

snippet randsequence
	randsequence(${1:production})
	    ${1}: ${2:item1} ${3:| item2};
	    $2: ${4:/* actions */};
	    $3: ${5:/* actions */};
	endsequence

# =============================================================================
# SOFT CONSTRAINTS
# =============================================================================

snippet soft_constraint
	constraint ${1:name}_c {
	    soft ${2:variable} == ${3:value};
	}

# =============================================================================
# DIST CONSTRAINTS (Advanced)
# =============================================================================

snippet dist_weight
	${1:variable} dist {
	    ${2:value1} := ${3:weight1},
	    ${4:value2} := ${5:weight2},
	    [${6:min}:${7:max}] := ${8:weight3}
	};

snippet dist_equal
	${1:variable} dist {
	    ${2:value1}, ${3:value2}, ${4:value3}
	};

# =============================================================================
# IMPLICATION CONSTRAINTS
# =============================================================================

snippet constraint_implication
	constraint ${1:name}_c {
	    ${2:condition} -> ${3:constraint};
	}

snippet constraint_if
	constraint ${1:name}_c {
	    if (${2:condition})
	        ${3:constraint1}
	    else
	        ${4:constraint2}
	}

# =============================================================================
# FOREACH IN CONSTRAINTS
# =============================================================================

snippet constraint_foreach
	constraint ${1:name}_c {
	    foreach (${2:array}[${3:i}])
	        ${2}[$3] ${4:inside {[0:10]}};
	}

# =============================================================================
# UNIQUE IN CONSTRAINTS
# =============================================================================

snippet constraint_unique
	constraint ${1:name}_c {
	    unique {${2:var1}, ${3:var2}, ${4:var3}};
	}

# =============================================================================
# INLINE RANDOMIZATION
# =============================================================================

snippet randomize_inline
	std::randomize(${1:variable}) with {
	    $1 ${2:inside {[0:100]}};
	};

# =============================================================================
# CROSS COVERAGE (Advanced)
# =============================================================================

snippet cross_binsof
	${1:name}_cross: cross ${2:cp1}, ${3:cp2} {
	    ignore_bins ${4:ignore} = binsof(${2}) intersect {${5:values}};
	}

snippet cross_iff
	${1:name}_cross: cross ${2:cp1}, ${3:cp2} iff (${4:condition});

# =============================================================================
# SYSTEM FUNCTIONS (Additional)
# =============================================================================

snippet countones
	\$countones(${1:expression})

snippet countbits
	\$countbits(${1:expression}, ${2:'1})

snippet onehot
	\$onehot(${1:expression})

snippet onehot0
	\$onehot0(${1:expression})

snippet isunknown
	\$isunknown(${1:expression})

snippet bits
	\$bits(${1:expression})

snippet typename
	\$typename(${1:expression})

snippet high
	\$high(${1:array})

snippet low
	\$low(${1:array})

snippet left
	\$left(${1:array})

snippet right
	\$right(${1:array})

snippet increment
	\$increment(${1:array})

snippet size
	\$size(${1:array}, ${2:dimension})

snippet dimensions
	\$dimensions(${1:array})

snippet unpacked_dimensions
	\$unpacked_dimensions(${1:array})

# =============================================================================
# SEVERITY SYSTEM TASKS
# =============================================================================

snippet fatal
	\$fatal(${1:finish_number}, "${2:message}", ${3:args});

snippet error
	\$error("${1:message}", ${2:args});

snippet warning
	\$warning("${1:message}", ${2:args});

snippet info
	\$info("${1:message}", ${2:args});

# =============================================================================
# UVM HDL ACCESS (uvm_hdl_read/force/deposit)
# =============================================================================

snippet uvm_hdl_read
	uvm_hdl_read("${1:hdl_path}", ${2:value});

snippet uvm_hdl_force
	uvm_hdl_force("${1:hdl_path}", ${2:value});

snippet uvm_hdl_release
	uvm_hdl_release("${1:hdl_path}");

snippet uvm_hdl_deposit
	uvm_hdl_deposit("${1:hdl_path}", ${2:value});

snippet uvm_hdl_check_path
	uvm_hdl_check_path("${1:hdl_path}");

snippet uvm_hdl_read_string
	uvm_hdl_read_string("${1:hdl_path}", ${2:str_value});

snippet uvm_hdl_force_string
	uvm_hdl_force_string("${1:hdl_path}", "${2:str_value}");

snippet uvm_hdl_deposit_string
	uvm_hdl_deposit_string("${1:hdl_path}", "${2:str_value}");

# =============================================================================
# UVM PHASE METHODS
# =============================================================================

snippet build_phase
	function void build_phase(uvm_phase phase);
	    super.build_phase(phase);
	    ${1}
	endfunction: build_phase

snippet pre_build_phase
	function void pre_build_phase(uvm_phase phase);
	    super.pre_build_phase(phase);
	    ${1}
	endfunction: pre_build_phase

snippet post_build_phase
	function void post_build_phase(uvm_phase phase);
	    super.post_build_phase(phase);
	    ${1}
	endfunction: post_build_phase

snippet connect_phase
	function void connect_phase(uvm_phase phase);
	    super.connect_phase(phase);
	    ${1}
	endfunction: connect_phase

snippet pre_connect_phase
	function void pre_connect_phase(uvm_phase phase);
	    super.pre_connect_phase(phase);
	    ${1}
	endfunction: pre_connect_phase

snippet post_connect_phase
	function void post_connect_phase(uvm_phase phase);
	    super.post_connect_phase(phase);
	    ${1}
	endfunction: post_connect_phase

snippet end_of_elaboration_phase
	function void end_of_elaboration_phase(uvm_phase phase);
	    super.end_of_elaboration_phase(phase);
	    ${1}
	endfunction: end_of_elaboration_phase

snippet pre_end_of_elaboration_phase
	function void pre_end_of_elaboration_phase(uvm_phase phase);
	    super.pre_end_of_elaboration_phase(phase);
	    ${1}
	endfunction: pre_end_of_elaboration_phase

snippet post_end_of_elaboration_phase
	function void post_end_of_elaboration_phase(uvm_phase phase);
	    super.post_end_of_elaboration_phase(phase);
	    ${1}
	endfunction: post_end_of_elaboration_phase

snippet start_of_simulation_phase
	function void start_of_simulation_phase(uvm_phase phase);
	    super.start_of_simulation_phase(phase);
	    ${1}
	endfunction: start_of_simulation_phase

snippet pre_start_of_simulation_phase
	function void pre_start_of_simulation_phase(uvm_phase phase);
	    super.pre_start_of_simulation_phase(phase);
	    ${1}
	endfunction: pre_start_of_simulation_phase

snippet post_start_of_simulation_phase
	function void post_start_of_simulation_phase(uvm_phase phase);
	    super.post_start_of_simulation_phase(phase);
	    ${1}
	endfunction: post_start_of_simulation_phase

snippet run_phase
	task run_phase(uvm_phase phase);
	    super.run_phase(phase);
	    ${1}
	endtask: run_phase

snippet pre_run_phase
	function void pre_run_phase(uvm_phase phase);
	    super.pre_run_phase(phase);
	    ${1}
	endfunction: pre_run_phase

snippet post_run_phase
	function void post_run_phase(uvm_phase phase);
	    super.post_run_phase(phase);
	    ${1}
	endfunction: post_run_phase

snippet extract_phase
	// Collect simulation data, statistics, etc.
	function void extract_phase(uvm_phase phase);
	    super.extract_phase(phase);
	    ${1}
	endfunction: extract_phase

snippet check_phase
	function void check_phase(uvm_phase phase);
	    super.check_phase(phase);
	    ${1}
	endfunction: check_phase


snippet report_phase
	function void report_phase(uvm_phase phase);
	    super.report_phase(phase);
	    ${1}
	endfunction: report_phase

snippet final_phase
	function void final_phase(uvm_phase phase);
	    super.final_phase(phase);
	    ${1}
	endfunction: final_phase
# Runtime Phases (12-phase triads)
snippet pre_reset_phase
	task pre_reset_phase(uvm_phase phase);
	    super.pre_reset_phase(phase);
	    ${1}
	endtask: pre_reset_phase

snippet reset_phase
	task reset_phase(uvm_phase phase);
	    super.reset_phase(phase);
	    ${1}
	endtask: reset_phase

snippet post_reset_phase
	task post_reset_phase(uvm_phase phase);
	    super.post_reset_phase(phase);
	    ${1}
	endtask: post_reset_phase

snippet pre_configure_phase
	task pre_configure_phase(uvm_phase phase);
	    super.pre_configure_phase(phase);
	    ${1}
	endtask: pre_configure_phase

snippet configure_phase
	task configure_phase(uvm_phase phase);
	    super.configure_phase(phase);
	    ${1}
	endtask: configure_phase

snippet post_configure_phase
	task post_configure_phase(uvm_phase phase);
	    super.post_configure_phase(phase);
	    ${1}
	endtask: post_configure_phase

snippet pre_main_phase
	task pre_main_phase(uvm_phase phase);
	    super.pre_main_phase(phase);
	    ${1}
	endtask: pre_main_phase

snippet main_phase
	task main_phase(uvm_phase phase);
	    super.main_phase(phase);
	    ${1}
	endtask: main_phase

snippet post_main_phase
	task post_main_phase(uvm_phase phase);
	    super.post_main_phase(phase);
	    ${1}
	endtask: post_main_phase

snippet pre_shutdown_phase
	task pre_shutdown_phase(uvm_phase phase);
	    super.pre_shutdown_phase(phase);
	    ${1}
	endtask: pre_shutdown_phase

snippet shutdown_phase
	task shutdown_phase(uvm_phase phase);
	    super.shutdown_phase(phase);
	    ${1}
	endtask: shutdown_phase

snippet post_shutdown_phase
	task post_shutdown_phase(uvm_phase phase);
	    super.post_shutdown_phase(phase);
	    ${1}
	endtask: post_shutdown_phase

# =============================================================================
# UVM PHASE METHODS (Optional Inline Completions)
# =============================================================================

snippet phase build_phase
	function void `expand('%:t:r')`::build_phase(uvm_phase phase);
	    // Purpose: create/configure components; do NOT call super
	    // Example:
	    // sqr = my_sequencer::type_id::create("sqr", this);
	    // drv = my_driver::type_id::create("drv", this);
	    // mon = my_monitor::type_id::create("mon", this);
	    // if (!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif))
	    //   `uvm_fatal(get_name(), "Virtual interface not found")
	    // uvm_config_db#(uvm_object_wrapper)::set(this, "sqr.main_phase", "default_sequence", my_sequence::type_id::get());
	    ${0}
	endfunction: build_phase

snippet phase connect_phase
	function void `expand('%:t:r')`::connect_phase(uvm_phase phase);
	    // Purpose: connect TLM ports/exports and analysis ports
	    // Example:
	    // drv.seq_item_port.connect(sqr.seq_item_export);
	    // mon.ap.connect(sb.analysis_export);
	    // if (is_active == UVM_ACTIVE) drv.seq_item_port.connect(sqr.seq_item_export);
	    super.connect_phase(phase);
	    ${0}
	endfunction: connect_phase



snippet phase end_of_elaboration_phase
	function void `expand('%:t:r')`::end_of_elaboration_phase(uvm_phase phase);
	    // Purpose: validate topology, print configuration
	    // Example:
	    // uvm_root::get().print_topology();
	    // uvm_config_db#(type)::dump();
	    super.end_of_elaboration_phase(phase);
	    ${0}
	endfunction: end_of_elaboration_phase


snippet phase start_of_simulation_phase
	function void `expand('%:t:r')`::start_of_simulation_phase(uvm_phase phase);
	    // Purpose: pre-sim setup/logging
	    // Example:
	    // `uvm_info(get_name(), "Start of simulation", UVM_LOW)
	    // uvm_report_server rs = uvm_report_server::get_server();
	    // rs.set_max_quit_count(0);
	    // uvm_root::get().set_timeout(1ms, 0);
	    // `uvm_info(get_name(), $sformatf("Seed=%0d", $get_initial_random_seed()), UVM_LOW)
	    super.start_of_simulation_phase(phase);
	    ${0}
	endfunction: start_of_simulation_phase

snippet phase run_phase
	task `expand('%:t:r')`::run_phase(uvm_phase phase);
	    // Purpose: time-based behavior, objections, stimulus
	    // Example:
	    // phase.raise_objection(this);
	    // fork
	    //   begin `uvm_do(req) end
	    //   begin monitor.run(); end
	    // join
	    // phase.drop_objection(this);
	    // `uvm_info(get_name(), "Run phase active", UVM_LOW)
	    super.run_phase(phase);
	    ${0}
	endtask: run_phase




snippet phase extract_phase
	function void `expand('%:t:r')`::extract_phase(uvm_phase phase);
	    // Purpose: collect data/statistics
	    // Example:
	    // sb.extract();
	    // void'($display("Extracting stats"));
	    // cov_db.sample();
	    super.extract_phase(phase);
	    ${0}
	endfunction: extract_phase


snippet phase check_phase
	function void `expand('%:t:r')`::check_phase(uvm_phase phase);
	    // Purpose: validate results (scoreboards, assertions)
	    // Example:
	    // if (!sb.is_pass()) `uvm_error(get_name(), "Scoreboard failed")
	    // `uvm_info(get_name(), $sformatf("Coverage=%0.2f", cov.get_inst_coverage()), UVM_LOW)
	    super.check_phase(phase);
	    ${0}
	endfunction: check_phase


snippet phase report_phase
	function void `expand('%:t:r')`::report_phase(uvm_phase phase);
	    // Purpose: emit reports/summaries
	    // Example:
	    // `uvm_info(get_name(), sb.format_results(), UVM_NONE)
	    // void'($display("Report: %s", get_full_name()));
	    // uvm_report_server::get_server().summarize();
	    super.report_phase(phase);
	    ${0}
	endfunction: report_phase



snippet phase final_phase
	function void `expand('%:t:r')`::final_phase(uvm_phase phase);
	    // Purpose: cleanup resources, finalize logs
	    // Example:
	    // void'($display("Finalizing"));
	    // if ($test$plusargs("auto_finish")) $finish;
	    super.final_phase(phase);
	    ${0}
	endfunction: final_phase



# Runtime Inline (two-choice) snippets
snippet phase pre_reset_phase
	task `expand('%:t:r')`::pre_reset_phase(uvm_phase phase);
	// Purpose: prepare for reset (stop drivers, clear state)
	// Example:
	// drv.stop(); mon.clear(); sb.reset();
	${0}
	endtask: pre_reset_phase

snippet phase reset_phase
	task `expand('%:t:r')`::reset_phase(uvm_phase phase);
	// Purpose: apply and hold reset
	// Example:
	// vif.rst_n <= 0; repeat (5) @(posedge vif.clk); vif.rst_n <= 1;
	${0}
	endtask: reset_phase

snippet phase post_reset_phase
	task `expand('%:t:r')`::post_reset_phase(uvm_phase phase);
	// Purpose: resume after reset (re-enable components)
	// Example:
	// drv.start(); mon.enable();
	${0}
	endtask: post_reset_phase

snippet phase pre_configure_phase
	task `expand('%:t:r')`::pre_configure_phase(uvm_phase phase);
	// Purpose: set configuration knobs
	// Example:
	// uvm_config_db#(int)::set(this, "sqr", "burst_len", 16);
	${0}
	endtask: pre_configure_phase

snippet phase configure_phase
	task `expand('%:t:r')`::configure_phase(uvm_phase phase);
	// Purpose: program DUT registers/modes via sequences
	// Example:
	// cfg_seq seq = cfg_seq::type_id::create("cfg_seq");
	// seq.start(sqr);
	${0}
	endtask: configure_phase

snippet phase post_configure_phase
	task `expand('%:t:r')`::post_configure_phase(uvm_phase phase);
	// Purpose: validate configuration completion
	// Example:
	// `uvm_info(get_name(), "Configuration completed", UVM_LOW)
	${0}
	endtask: post_configure_phase

snippet phase pre_main_phase
	task `expand('%:t:r')`::pre_main_phase(uvm_phase phase);
	// Purpose: prepare for main stimulus (seed, counters)
	// Example:
	// void'($urandom(seed));
	${0}
	endtask: pre_main_phase

snippet phase main_phase
	task `expand('%:t:r')`::main_phase(uvm_phase phase);
	// Purpose: primary stimulus with objections
	// Example:
	// phase.raise_objection(this);
	// my_seq seq = my_seq::type_id::create("seq");
	// seq.start(sqr);
	// phase.drop_objection(this);
	${0}
	endtask: main_phase

snippet phase post_main_phase
	task `expand('%:t:r')`::post_main_phase(uvm_phase phase);
	// Purpose: cleanup after main stimulus
	// Example:
	// drv.flush(); sb.summarize();
	${0}
	endtask: post_main_phase

snippet phase pre_shutdown_phase
	task `expand('%:t:r')`::pre_shutdown_phase(uvm_phase phase);
	// Purpose: prepare for shutdown (stop new transactions)
	// Example:
	// drv.stop_issuance();
	${0}
	endtask: pre_shutdown_phase

snippet phase shutdown_phase
	task `expand('%:t:r')`::shutdown_phase(uvm_phase phase);
	// Purpose: drain pipelines and flush outstanding items
	// Example:
	// phase.raise_objection(this);
	// wait_for_drain();
	// phase.drop_objection(this);
	${0}
	endtask: shutdown_phase

snippet phase post_shutdown_phase
	task `expand('%:t:r')`::post_shutdown_phase(uvm_phase phase);
	// Purpose: finalize run (close files, release handles)
	// Example:
	// `uvm_info(get_name(), "Shutdown complete", UVM_LOW)
	${0}
	endtask: post_shutdown_phase


# =============================================================================
# UVM PHASE METHODS (Extern Completions)
# Usage per phase (declarations only; implement outside the class):
# - build_phase: extern function; implementation creates/configures components.
# - connect_phase: extern function; implementation connects TLM/analysis ports.
# - start_of_simulation_phase: extern function; implementation performs pre-sim setup.
# Examples:
# - Class declaration:
#   class my_component extends uvm_component;
#     extern function void build_phase(uvm_phase phase);
#     extern function void connect_phase(uvm_phase phase);
#     extern task run_phase(uvm_phase phase);
#   endclass
# - Implementation outside class:
#   function void my_component::build_phase(uvm_phase phase);
#     mon = my_monitor::type_id::create("mon", this);
#   endfunction
#   function void my_component::connect_phase(uvm_phase phase);
#     drv.seq_item_port.connect(sqr.seq_item_export);
#   endfunction
#   task my_component::run_phase(uvm_phase phase);
#     phase.raise_objection(this);
#     // stimulus
#     phase.drop_objection(this);
#   endtask
# - run_phase: extern task; implementation drives stimulus and objections.
# - extract/check/report/final: extern functions; implementations collect, check,
#   report, and cleanup.
# =============================================================================

snippet extern build_phase
	extern function void build_phase(uvm_phase phase);

snippet extern connect_phase
	extern function void connect_phase(uvm_phase phase);

snippet extern end_of_elaboration_phase
	extern function void end_of_elaboration_phase(uvm_phase phase);

snippet extern start_of_simulation_phase
	extern function void start_of_simulation_phase(uvm_phase phase);

snippet extern run_phase
	extern task run_phase(uvm_phase phase);

snippet extern extract_phase
	extern function void extract_phase(uvm_phase phase);

snippet extern check_phase
	extern function void check_phase(uvm_phase phase);

snippet extern report_phase
	extern function void report_phase(uvm_phase phase);

snippet extern final_phase
	extern function void final_phase(uvm_phase phase);


snippet extern pre_reset_phase
	extern task pre_reset_phase(uvm_phase phase);

snippet extern reset_phase
	extern task reset_phase(uvm_phase phase);

snippet extern post_reset_phase
	extern task post_reset_phase(uvm_phase phase);

snippet extern pre_configure_phase
	extern task pre_configure_phase(uvm_phase phase);

snippet extern configure_phase
	extern task configure_phase(uvm_phase phase);

snippet extern post_configure_phase
	extern task post_configure_phase(uvm_phase phase);

snippet extern pre_main_phase
	extern task pre_main_phase(uvm_phase phase);

snippet extern main_phase
	extern task main_phase(uvm_phase phase);

snippet extern post_main_phase
	extern task post_main_phase(uvm_phase phase);

snippet extern pre_shutdown_phase
	extern task pre_shutdown_phase(uvm_phase phase);

snippet extern shutdown_phase
	extern task shutdown_phase(uvm_phase phase);

snippet extern post_shutdown_phase
	extern task post_shutdown_phase(uvm_phase phase);



#######
snippet uvm_objection
	    phase.raise_objection(this);
	    \`uvm_info(${1:get_full_name()},"${2:main_phase} started, objection raised.", ${3:UVM_NONE})
	    $0
	    phase.drop_objection(this);
	    uvm_info($1, "$2 finished, objection dropped ", $3)
snippet objection
	    phase.raise_objection(this);
	    \`uvm_info(${1:get_full_name()},"${2:main_phase} started, objection raised.", ${3:UVM_NONE})
	    $0
	    phase.drop_objection(this);
	    uvm_info($1, "$2 finished, objection dropped ", $3)