UVM接口信号同步机制

class bus_config extends uvm_object;
    virtual bus_interface bus_if;
    
    // 等待指定时钟周期
    task wait_for_clock(int cycles=1);
        repeat(cycles) @(posedge bus_if.clk);
    endtask
    
    // 等待复位信号有效
    task wait_for_reset();
        @(posedge bus_if.reset);
    endtask
endclass

class transaction extends uvm_sequence_item;
    `uvm_object_utils(transaction)
    
    rand logic [31:0] addr;
    rand logic [31:0] write_data;
    rand bit read;
    rand int delay;
    
    bit error;
    logic [31:0] read_data;
    
    constraint addr_alignment {
        addr[1:0] == 0;  // 32位地址对齐
    }
    
    constraint delay_range {
        delay inside {[1:20]};
    }
endclass

class bus_seq extends uvm_sequence #(transaction);
    `uvm_object_utils(bus_seq)
    
    transaction txn;
    bus_config bus_cfg;
    rand int limit = 25;
    
    task body();
        int i = 5;
        txn = transaction::type_id::create("txn");
        
        // 获取配置对象
        if(!uvm_config_db #(bus_config)::get(null, get_full_name(), 
           "config", bus_cfg)) begin
            `uvm_error("SEQ_ERROR", "总线配置对象获取失败")
        end
        
        repeat (limit) begin
            start_item(txn);
            if(!txn.randomize() with {
                addr inside {[32'h0010_0000:32'h0010_001C];
            }) begin
                `uvm_error("RAND_ERROR", "事务随机化失败")
            end
            finish_item(txn);
            
            // 动态调整时钟等待周期
            bus_cfg.wait_for_clock(i);
            i++;
            
            `uvm_info("SEQ_DEBUG", $sformatf("读取数据: 0x%h", 
                     txn.read_data), UVM_LOW)
        end
    endtask
endclass